Leadless semiconductor packages such as Quad Flat Nonleaded, QFN, or Thin Small Outline Nonleaded, TSON, are IC packages with lower cost, higher thermal conductivity and smaller footprint. When using leadless leadframes as chip carriers for leadless semiconductor packages, the bottom surfaces of the inner leads are used as external terminals. There is no need for outer leads extending from the sides of the encapsulant so that the dimension of the semiconductor package can further be shrunk. Such a leadless semiconductor package is disclosed in U.S. Pat. No. 6,143,981.
However, the materials of leadframes are normally etchable metals for easy leadframe formation such as copper, iron, or their alloys, which are easily suffered from corrosions. Therefore, an electroplated layer is plated on the exposed surfaces of the inner leads such as nickel/gold, tin, or solder to prevent corrosions and to enhance soldering adhesion to external printed circuit boards. The manufacturing processes of a leadless semiconductor package normally include “die attaching”, “electrically connecting”, “encapsulating”, “electroplating”, and “singulation” in turn. An electroplating step is performed after encapsulation, the electroplated layer is disposed on the bottom surface of the inner leads and is protruded from the bottom of the encapsulant. The related packaging processes have been disclosed in Taiwan Patent No. 1244745, “A leadless leadframe for manufacturing a leadless package and its processes”.
According to conventional processes, the electroplated layer for external terminals is protruded from the bottom surface of the encapsulant. However, the electroplated layers of the leadless semiconductor packages can easily be damaged during the shipping, handling, or storage. Moreover, since there is no solder mask on the inner leads, the electroplated layer can easily be plated on the peripheries of the inner leads leading to electrical shorts.
Furthermore, another issue of the conventional leadless semiconductor packages is most of the bottom surfaces and sides of the inner leads of a leadframe are exposed from the bottom surface of the encapsulant, there is not enough adhesion between the leadframe and the encapsulant. The inner leads will easily separate from the bottom surface of the encapsulant due to the induced thermal cycles during chip operations.